1. Field of the Invention
The present invention relates to a method of manufacturing a MOS transistor, and more particularly, to a method of manufacturing a CMOS transistor by using a SOI (silicon on insulator) substrate to increase integration degree.
2. Description of the Related Art
FIGS. 1 to 5 are cross sectional views for explaining a method of manufacturing a conventional MOS transistor, such as a p-channel MOS transistor.
Referring to FIG. 1, an active region where a MOS transistor is to be formed is defined by forming an element isolation layer 110 on an n-type semiconductor substrate 100. Alternatively, instead of the n-type semiconductor substrate 100, a p-type semiconductor substrate may be used. In this case, an n-type well region is formed on the p-type semiconductor substrate.
Next, a gate stack is formed by subsequently stacking a gate insulating layer pattern 120 and a gate conductive layer pattern 130 on the active region of the substrate 100. The gate stack is disposed to cover a channel region in an upper portion of the semiconductor substrate 100.
Referring to FIG. 2, in order to reduce a short channel effect, a halo ion implanting process is performed. As a result, a halo impurity region 141 is formed to surround a channel region under the gate insulating layer pattern 120 by implanting n-type impurity ions in the substrate 100 in a slanted direction thereof.
Referring to FIG. 3, a first ion implanting process is performed by implanting p-type impurity ions in the substrate 100. As a result, source/drain extension regions 142 are formed in the substrate at both sides of the gate 130. In some cases, the first ion implanting process may be performed prior to the halo ion implanting process.
In addition, although not shown in the figure, an oxide layer may be formed as an ion implanting buffer layer on a surface of the substrate 100 prior to the second ion implanting process.
Referring to FIG. 4, gate spacer layers 150 are formed on side walls of the gate conductive layer 130. Next, a second ion implanting process is performed by implanting p-type impurity ions by using the gate spacer layers 150 as an ion implanting barrier. As a result, source/drain regions 143 are formed in the substrate 100 at the respective sides of the gate spacer layers 150.
Referring to FIG. 5, a MOS transistor is completed by performing a general silicide process forming metal silicide layers 160 on the source/drain regions 143 and the gate conductive layer pattern 130 and subsequently performing a general metallization process.
The aforementioned method of manufacturing the MOS transistor may be adapted to an n-channel MOS transistor as well as the aforementioned p-channel MOS transistor.
However, as recognized by the present inventor, in a CMOS transistor where p-type and n-channel MOS transistors are formed parallel to each other in the same layer in a single substrate, since an element isolation layer needs to be formed to isolate the p-type and n-channel MOS transistors, there is a limitation to increase integration degree.